Author: admin

Kernel-Level PMIC Interaction: Interfacing with Android’s Power Management IC Drivers
Introduction to Power Management ICs (PMICs) in Android Systems

Power Management Integrated Circuits (PMICs) are the unsung heroes of modern mobile devices. These highly integrated chips manage nearly every aspect of power delivery within an Android smartphone or tablet, from charging the battery and supplying stable voltages to various components (CPU, GPU, memory, peripherals) to handling power-on/off sequences and thermal management. For advanced developers, reverse engineers, and hardware hackers, understanding and interacting with a device’s PMIC at the kernel level opens up a world of possibilities for custom power optimizations, debugging obscure hardware issues, and even enabling features not officially supported.

This article delves into the intricacies of kernel-level PMIC interaction, focusing on how Android’s Linux kernel interfaces with these critical components. We’ll explore methods for identifying PMICs, understanding their driver frameworks, and even direct register manipulation (with extreme caution).

Understanding PMIC Architecture and Kernel Interaction

The Role of PMICs

A PMIC typically integrates a wide array of power management functionalities, including:
- Battery Charging Circuitry: Managing charge cycles, current, and voltage for Li-Ion batteries.
- Voltage Regulators: Step-down (buck) and step-up (boost) converters, Low-Dropout (LDO) regulators providing various voltage rails to different system components.
- GPIOs and Interrupts: General-purpose input/output pins for controlling external components and interrupt lines for system events.
- Real-Time Clock (RTC): Maintaining system time even when the device is off.
- Power Sequencing: Orchestrating the power-on and power-off sequence of different components.
The Linux Kernel’s Regulator Framework

In the Android Linux kernel, PMICs are primarily managed through the ‘regulator’ framework. This generic framework abstracts the complexities of various PMIC hardware into a unified software interface. It allows device drivers to request specific voltage rails, enable/disable regulators, and adjust output voltages without needing to know the low-level PMIC specific registers.

PMIC drivers register their available regulators with this framework, often parsing their configuration from the Device Tree Blob (DTB).

Identifying Your Device’s PMIC and Drivers

The first step to interacting with your PMIC is identifying it. This often involves a combination of hardware analysis and kernel log inspection.

1. Physical Inspection & Schematics (If Available)

If you have access to board schematics or a boardview, you can directly locate the PMIC chip. Common PMIC vendors include Qualcomm (PMxxxx series), MediaTek (MTxxxx), Texas Instruments (TPSxxxx), and Broadcom. The PMIC is usually a complex BGA package near the main SoC.

2. Kernel Logs (dmesg)

After booting, the kernel prints messages during device enumeration and driver probing. Look for entries related to ‘pmic’, ‘regulator’, ‘qcom,pm’, ‘mt-pmic’, etc. Use `dmesg` or inspect `/proc/last_kmsg`:
```
adb shell dmesg | grep -i pmicadb shell dmesg | grep -i regulator
```
You might see output like:
```
[    1.234567] qcom-pmic-arb: PMIC arbiter initialized[    1.235000] pm8953-regulators: Initialized 12 regulators
```
This indicates a Qualcomm PM8953 PMIC is present and its regulator driver has initialized.

3. Device Tree Blob (DTB) Analysis

The DTB (Device Tree Blob) is crucial. It describes the hardware components to the kernel. On many Android devices, the DTB is located in the boot partition. Extracting and decompressing it allows you to inspect PMIC-related nodes.
```
# On your host machine with `dtc` (device tree compiler) installedfdtoverlay -i your_dtb_file.dtb -o decompiled.dts
```
Search `decompiled.dts` for common PMIC nodes or compatible strings:
- `compatible = “qcom,pm8953”;`
- `regulators { … };`
- `i2c-bus { … pmic_addr … };`
These nodes will define the I2C/SPI address of the PMIC, its available regulators, and their default configurations.

Interacting with PMIC Regulators via sysfs

The `regulator` framework exposes much of its functionality through `sysfs`, making basic interaction relatively straightforward from userspace (with root privileges).

Listing Regulators

The `/sys/class/regulator/` directory lists all registered regulators. Each subdirectory corresponds to a specific regulator.
```
adb shell ls -l /sys/class/regulator/
```
You’ll see regulators named like `regulator.0`, `regulator.1`, or descriptive names if provided by the driver (e.g., `vdd_cpu`, `ldo1`).

Reading Regulator Status

Navigate into a regulator’s directory to inspect its properties:
```
adb shellcd /sys/class/regulator/regulator.0 # Or specific name like vdd_cpuadb shellcat nameadb shellcat microvolts_setadb shellcat state
```
Common files include:
- `name`: The name of the regulator.
- `microvolts_set`: The currently set voltage in microvolts.
- `microvolts_max`: Maximum allowed voltage.
- `microvolts_min`: Minimum allowed voltage.
- `state`: Current state (e.g., ‘enabled’, ‘disabled’).
Adjusting Regulator Voltage (CAUTION!)

You can often change the voltage of a regulator by echoing a new value to `microvolts_set`. WARNING: Incorrect voltage settings can instantly damage hardware or cause system instability. Proceed with extreme caution and only on non-critical test devices.
```
# EXAMPLE ONLY - DO NOT BLINDLY EXECUTECurrent voltage:adb shell cat /sys/class/regulator/vdd_cpu/microvolts_set  # e.g., 900000 (900mV)# Attempt to set a new voltage (e.g., 850mV)adb shell echo 850000 > /sys/class/regulator/vdd_cpu/microvolts_set# Verify the changeadb shell cat /sys/class/regulator/vdd_cpu/microvolts_set
```
If the PMIC supports the requested voltage and it’s within min/max limits, the change will take effect immediately.

Direct PMIC Register Access (Advanced and Highly Risky)

While `sysfs` provides an abstraction, there are scenarios (e.g., reverse engineering undocumented features, very low-level debugging) where direct PMIC register access is necessary. This typically involves writing a custom kernel module or leveraging existing debug interfaces.

Method: Custom Kernel Module for I2C/SPI Access

Most PMICs communicate with the SoC via I2C or SPI. To access registers directly, you’d write a simple kernel module that binds to the appropriate I2C/SPI device.

Here’s a simplified C code snippet demonstrating how a kernel module might read/write to an I2C-connected PMIC. This assumes you know the I2C bus number and the PMIC’s I2C address.
```
#include <linux/module.h>#include <linux/kernel.h>#include <linux/i2c.h>#include <linux/delay.h>#define PMIC_I2C_BUS_NUM  7    // Example: I2C bus 7#define PMIC_I2C_ADDR     0x60 // Example: PMIC I2C slave address#define PMIC_REG_ID       0x00 // Example: A dummy register address for ID#define PMIC_REG_CTRL     0x01 // Example: A dummy control register#define PMIC_REG_VAL      0xAA // Example: Value to write to control registerstatic struct i2c_client *pmic_i2c_client = NULL;static int pmic_probe(struct i2c_client *client, const struct i2c_device_id *id){    pr_info("PMIC: Probing I2C device at addr 0x%xn", client->addr);    pmic_i2c_client = client;    return 0;}static int pmic_remove(struct i2c_client *client){    pr_info("PMIC: Removing I2C devicen");    pmic_i2c_client = NULL;    return 0;}static const struct i2c_device_id pmic_id[] = {    { "my_pmic_device", 0 },    { }};MODULE_DEVICE_TABLE(i2c, pmic_id);static struct i2c_driver pmic_driver = {    .driver = {        .name   = "my_pmic_driver",        .owner  = THIS_MODULE,    },    .probe      = pmic_probe,    .remove     = pmic_remove,    .id_table   = pmic_id,};static ssize_t pmic_read_reg_show(struct class *class, struct class_attribute *attr, char *buf){    int ret;    u8 reg_val;    if (!pmic_i2c_client)        return sprintf(buf, "PMIC I2C client not foundn");    // Example: Read PMIC_REG_ID    ret = i2c_smbus_read_byte_data(pmic_i2c_client, PMIC_REG_ID);    if (ret < 0) {        pr_err("PMIC: Failed to read register 0x%xn", PMIC_REG_ID);        return sprintf(buf, "Error reading registern");    }    reg_val = (u8)ret;    pr_info("PMIC: Read register 0x%x = 0x%xn", PMIC_REG_ID, reg_val);    return sprintf(buf, "0x%02xn", reg_val);}static ssize_t pmic_write_reg_store(struct class *class, struct class_attribute *attr, const char *buf, size_t count){    int ret;    u8 val_to_write;    if (!pmic_i2c_client)        return -EIO;    if (kstrtou8(buf, 0, &val_to_write) < 0)        return -EINVAL;    // Example: Write to PMIC_REG_CTRL    ret = i2c_smbus_write_byte_data(pmic_i2c_client, PMIC_REG_CTRL, val_to_write);    if (ret < 0) {        pr_err("PMIC: Failed to write 0x%x to register 0x%xn", val_to_write, PMIC_REG_CTRL);        return ret;    }    pr_info("PMIC: Wrote 0x%x to register 0x%xn", val_to_write, PMIC_REG_CTRL);    return count;}// Create sysfs entries to interact with our module (optional but useful)static struct class *pmic_class;static CLASS_ATTR_RW(pmic_read_reg);static CLASS_ATTR_WO(pmic_write_reg);static int __init pmic_module_init(void){    int ret;    // Register our I2C driver    ret = i2c_add_driver(&pmic_driver);    if (ret) {        pr_err("PMIC: Failed to add I2C drivern");        return ret;    }    // Create a sysfs class for user interaction    pmic_class = class_create(THIS_MODULE, "pmic_debug");    if (IS_ERR(pmic_class)) {        pr_err("PMIC: Failed to create sysfs classn");        i2c_del_driver(&pmic_driver);        return PTR_ERR(pmic_class);    }    // Create sysfs files for read/write    ret = class_create_file(pmic_class, &class_attr_pmic_read_reg);    if (ret) {        pr_err("PMIC: Failed to create pmic_read_reg filen");        class_destroy(pmic_class);        i2c_del_driver(&pmic_driver);        return ret;    }    ret = class_create_file(pmic_class, &class_attr_pmic_write_reg);    if (ret) {        pr_err("PMIC: Failed to create pmic_write_reg filen");        class_remove_file(pmic_class, &class_attr_pmic_read_reg);        class_destroy(pmic_class);        i2c_del_driver(&pmic_driver);        return ret;    }    pr_info("PMIC: Module loaded successfully. Check /sys/class/pmic_debug/n");    return 0;}static void __exit pmic_module_exit(void){    class_remove_file(pmic_class, &class_attr_pmic_write_reg);    class_remove_file(pmic_class, &class_attr_pmic_read_reg);    class_destroy(pmic_class);    i2c_del_driver(&pmic_driver);    pr_info("PMIC: Module unloadedn");}module_init(pmic_module_init);module_exit(pmic_module_exit);MODULE_LICENSE("GPL");MODULE_AUTHOR("Your Name");MODULE_DESCRIPTION("A kernel module for direct PMIC register interaction");
```
To compile and load this module:
1. Set up an Android kernel build environment.
2. Compile the `.c` file into a `.ko` (kernel object) module.
3. Push the `.ko` to your rooted Android device:
```
adb push my_pmic_driver.ko /data/local/tmp/
```
4. Load the module:
```
adb shellinsmod /data/local/tmp/my_pmic_driver.ko
```
5. Interact via sysfs:
```
adb shellcat /sys/class/pmic_debug/pmic_read_regadb shell echo 0xAB > /sys/class/pmic_debug/pmic_write_reg
```
Important Note: The `PMIC_I2C_BUS_NUM` and `PMIC_I2C_ADDR` must be correct for your specific device and PMIC. Incorrect values can lead to system freezes or unintended writes to other I2C devices. You will need to determine these from your DTB or kernel logs. The `i2c_smbus_*` functions are typically used for PMIC interactions.

Practical Use Cases and Safety Considerations

Use Cases:
- Power Optimization: Fine-tuning voltage rails to undervolt components for lower power consumption or overvolt for stability/performance (risky).
- Debugging: Diagnosing power-related reboots, freezes, or unusual behavior by monitoring PMIC status registers.
- Reverse Engineering: Understanding undocumented PMIC features, such as custom power modes, charging logic, or hardware interaction through specific GPIOs.
- Hardware Enablement: Initializing or configuring PMIC features that might be disabled or misconfigured by default.
Safety and Precautions:
- Backup Your Device: Always have a full backup before attempting kernel-level modifications.
- Test Environment: Perform experiments on non-critical, expendable hardware first.
- Voltage Ranges: Stick within manufacturer-specified voltage ranges when adjusting regulators. Going too high or too low can permanently damage components.
- Current Limiting: If working on the bench, use a current-limited power supply to prevent catastrophic failures during unexpected short circuits or high current draw.
- Kernel Knowledge: A solid understanding of Linux kernel device drivers, I2C/SPI protocols, and the Device Tree is essential.
Conclusion

Interfacing with Android’s Power Management IC drivers at the kernel level is a powerful, yet challenging, endeavor. From leveraging the well-structured `regulator` framework through `sysfs` to delving into direct I2C/SPI register manipulation via custom kernel modules, the possibilities for advanced power management and hardware interaction are vast. While the rewards of such low-level control are significant, the risks are equally high. Always proceed with a thorough understanding of the underlying hardware and software, prioritize safety, and meticulously verify every step. Mastering PMIC interaction is a hallmark of truly deep Android hardware reverse engineering.
May 29, 2026
How to Directly Manipulate Android PMIC Registers: A Practical Guide for Hardware Hacking
Introduction to PMIC Manipulation

Power Management Integrated Circuits (PMICs) are critical components in modern Android devices, responsible for managing virtually all aspects of power delivery, battery charging, voltage regulation, and system power states. Gaining direct control over PMIC registers can unlock advanced hardware hacking, reverse engineering, and custom optimization capabilities. This guide delves into the practical methods for identifying, accessing, and manipulating PMIC registers on Android devices, covering both software-based and advanced hardware-based techniques.

What is a PMIC?

A PMIC is a specialized IC that integrates multiple power management functions into a single chip. These functions typically include DC-DC converters, low-dropout regulators (LDOs), battery charge controllers, power-on reset generators, and various protection circuits. PMICs communicate with the System-on-Chip (SoC) primarily via I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface) buses, allowing the operating system to dynamically control power rails and monitor battery status.

Prerequisites for PMIC Hacking

Before embarking on PMIC manipulation, several prerequisites are essential to ensure a successful and safe endeavor:
- Rooted Android Device: Full root access is mandatory for software-based register access, allowing kernel module loading and direct device file manipulation.
- Access to Device Tree/Kernel Source: Understanding your device’s device tree (DTS/DTB) is crucial for identifying PMIC addresses and configurations. Kernel source provides insights into driver implementations.
- Hardware Tools (for advanced techniques): Soldering iron, multimeter, logic analyzer (e.g., Saleae Logic), JTAG/SWD debugger (e.g., J-Link, ST-Link, OpenOCD-compatible adapter), and a breakout board or test clips.
- Linux Command Line Proficiency: Familiarity with basic Linux commands, especially those for interacting with device files and I2C utilities.
- Datasheet Access (if possible): The PMIC datasheet is the ultimate reference for register maps and functionality. However, these are often proprietary and difficult to obtain for consumer devices.
Identifying Your Device’s PMIC

The first step is to identify the specific PMIC model used in your Android device. This information is vital for finding relevant documentation or making educated guesses about register layouts.
- Kernel Logs (`dmesg`): After booting, the kernel often logs PMIC initialization details. You can find this by running adb shell dmesg | grep -i pmic or adb shell dmesg | grep -i power.
- Device Tree Source (`.dts`, `.dtb`): If you have access to your device’s kernel source or a decompiled DTB, the PMIC will be explicitly defined. Look for nodes like pmic@<address> under an I2C bus controller.
- Physical Inspection: The PMIC chip is usually a prominent IC near the SoC or battery connector. Its markings can reveal the manufacturer (e.g., Qualcomm, MediaTek, NXP) and model number. A magnifying glass or microscope can assist in reading tiny print.
Software-Based PMIC Register Access (I2C-dev)

For most Android devices, the PMIC communicates over an I2C bus. Linux provides the i2c-dev subsystem and user-space tools to interact with these buses directly, provided you have root access and the necessary kernel modules are loaded.

Locating the I2C Bus

First, identify the I2C bus associated with your PMIC. On a rooted device, list available I2C devices:
```
adb shell ls -l /dev/i2c-*
```
This might output something like /dev/i2c-0, /dev/i2c-1, etc. You’ll need to determine which bus the PMIC resides on. Often, bus 0 or 1 is dedicated to critical components. You can sometimes infer this from kernel logs or device tree. Let’s assume /dev/i2c-1 for this example.

Using i2c-tools

The i2c-tools package (specifically i2cdetect, i2cget, i2cset) provides utilities for interacting with I2C devices. You may need to compile these for your device’s architecture or push pre-built binaries.

Detecting PMIC Address

PMICs typically have fixed I2C addresses. You can scan a bus to identify active devices:
```
adb shell i2cdetect -y 1
```
This will show a grid. Look for an address that corresponds to your PMIC (e.g., 0x48, 0x68). If the datasheet is unavailable, this step helps confirm its presence.

Reading a PMIC Register

To read the value of a specific register (e.g., register 0x01) from a PMIC at address 0x48 on bus 1:
```
adb shell i2cget -y 1 0x48 0x01
```
This command reads one byte. The output might be something like 0xCC.

Writing to a PMIC Register

To write a new value (e.g., 0x55) to register 0x02 of the PMIC at address 0x48 on bus 1:
```
adb shell i2cset -y 1 0x48 0x02 0x55
```
This command writes one byte. Always exercise extreme caution when writing to registers, as incorrect values can lead to system instability, crashes, or even permanent damage.

Hardware-Based PMIC Register Access (Advanced Techniques)

When software-based methods are insufficient, or if the device is unbootable, direct hardware intervention becomes necessary.

The Need for Hardware Access

Software-based I2C tools rely on the operating system’s drivers. If the PMIC driver is heavily customized, restricted, or if you need to debug power-related issues before the OS boots, hardware access provides a more granular and direct control path.

Snooping I2C Communication with a Logic Analyzer

A logic analyzer can passively monitor the I2C SDA (data) and SCL (clock) lines. This allows you to observe the communication between the SoC and the PMIC in real-time. By analyzing boot-up sequences, power state changes, or charging cycles, you can reverse engineer the I2C addresses, register access patterns, and data values used by the device’s firmware. This is invaluable when datasheets are unavailable.

Steps:
1. Locate the I2C lines: Identify test points or solder wires directly to the PMIC pins for SDA and SCL.
2. Connect logic analyzer: Attach probes to SDA, SCL, and ground.
3. Capture data: Power on the device and record the I2C traffic using the logic analyzer software.
4. Analyze: Use the software’s I2C decoder to interpret the captured data, revealing addresses, read/write commands, and register values.
Direct I2C Control via JTAG/SWD Debugger

Advanced hardware debuggers like JTAG or SWD allow you to halt the SoC, read/write its memory, and directly manipulate peripheral registers. Many SoCs integrate an I2C master controller whose registers are memory-mapped. By writing to these memory addresses, you can control the I2C bus directly, independent of the Android OS.

Conceptual Steps (using OpenOCD with JTAG/SWD):
1. Physical Connection: Identify JTAG/SWD test points on the PCB and solder fine wires or use a pogo pin adapter. Connect your JTAG/SWD debugger (e.g., an FT2232H-based adapter) to these points and to your host PC.
2. OpenOCD Configuration: Create an OpenOCD configuration file (`.cfg`) specific to your SoC and debugger.
3. Connect and Halt: Start OpenOCD and connect to the target. Halt the CPU to prevent it from interfering with your I2C operations.
4. Memory-Mapped I2C Access: Consult your SoC’s technical reference manual to find the base address and register map of its I2C controller. You’ll typically find registers for:
  - I2C Control Register (enable, clock speed)
  - I2C Status Register (busy, acknowledge, errors)
  - I2C Address Register (slave address)
  - I2C Data Register (read/write data)
  - I2C Command Register (start, stop, read, write)
5. Issue I2C Commands: Use OpenOCD’s mdw (memory display word), mwb (memory write byte) commands (or similar) to directly manipulate these memory-mapped I2C registers, mimicking the I2C protocol to read from or write to the PMIC. For example, to initiate a write:
  - Write the PMIC slave address (with write bit) to the I2C address register.
  - Write the PMIC register address to the I2C data register.
  - Write data to the I2C data register.
  - Toggle the start/stop/write bits in the I2C command register.
This method provides the most powerful control but requires deep knowledge of the SoC’s internal architecture and I2C controller implementation.

Practical Applications and Use Cases

Direct PMIC register manipulation opens up a range of possibilities:
- Battery Charging Profiles: Alter charging current, voltage limits, or temperature thresholds for faster charging (at your own risk) or extended battery life.
- Voltage Rail Adjustment: Fine-tune voltage rails for specific components to undervolt for power savings or overvolt for stability/performance (if supported and safe).
- Thermal Management: Modify temperature thresholds that trigger throttling, potentially allowing devices to run hotter for longer, or conversely, enforce stricter thermal limits.
- Debugging Power Issues: Read status registers to diagnose power-related problems, identify faulty components, or understand unexpected power drains.
Risks and Ethical Considerations

Manipulating PMIC registers carries significant risks:
- Device Bricking: Incorrect register values can render your device permanently inoperable.
- Overheating/Damage: Incorrect voltage or current settings can lead to component damage, overheating, and fire hazards.
- Warranty Voidance: Hardware modifications and extensive software changes will void your device’s warranty.
- Legal Implications: Ensure your activities comply with local laws and do not infringe on intellectual property rights.
Conclusion

Directly manipulating Android PMIC registers is a challenging but rewarding endeavor for hardware hackers and reverse engineers. Whether through software tools like i2c-tools or advanced hardware techniques involving logic analyzers and JTAG/SWD debuggers, gaining control over a device’s power management core offers unparalleled insights and customization potential. Always proceed with caution, understanding the risks involved, and prioritizing safety to prevent irreversible damage to your device.
May 29, 2026
Case Study: Reverse Engineering a Samsung Galaxy S Series PMIC for Custom Firmware Control
Introduction: Unlocking Power Beyond Android’s Default

Power Management Integrated Circuits (PMICs) are the unsung heroes of modern mobile devices, meticulously orchestrating power delivery to every component, from the CPU to the display backlight. In Android devices, PMICs are crucial for battery charging, voltage regulation, and low-power states. This case study delves into the intricate world of reverse engineering a PMIC found in a Samsung Galaxy S series device, with the ultimate goal of gaining custom firmware control over its operations. Such control can enable advanced power-saving techniques, custom charging profiles, or even novel hardware interactions for specialized applications.

Samsung Galaxy S devices often feature PMICs from various manufacturers, including Qualcomm (PMI/PM), Samsung’s own S2MP series, or sometimes STMicroelectronics. Our focus will be on a hypothetical S2MPxxx series PMIC, commonly found in Exynos-based variants, though the principles apply broadly to other PMICs and device architectures.

Phase 1: Identifying the PMIC and Initial Reconnaissance

Physical Inspection and Chip Identification

The first step in any hardware reverse engineering endeavor is physical inspection. Disassembling a Samsung Galaxy S device reveals its main logic board. The PMIC is typically a prominent chip, often located near the battery connector or the SoC, and might have markings like “S2MPxxx” or “PMxxx”. High-resolution images or a microscope are invaluable here.

Once identified, the standard procedure is to search for a public datasheet using the observed part number. However, for many smartphone components, especially those integrated deeply into proprietary designs, public datasheets are rare. This necessitates inferring functionality through software analysis.

The PMIC’s Communication Bus

PMICs primarily communicate with the main System-on-Chip (SoC) via either I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface) buses. I2C is more common for PMICs due to its simplicity and suitability for slower control signals. Identifying the bus and its address is paramount.

Phase 2: Software-Based PMIC Interaction Discovery

Without a datasheet, the Android kernel source code becomes our primary reference. OEMs like Samsung release kernel sources under GPL, which can be a treasure trove of information.

Kernel Source Analysis: Unveiling the Drivers

Navigate to the kernel’s power management subsystems. Typical paths include drivers/power/supply/, drivers/regulator/, or specific SoC vendor directories (e.g., drivers/soc/samsung/). Search for files matching your PMIC’s identified part number or common PMIC driver names.

For an S2MPxxx PMIC, you might find drivers like s2mp_charger.c, s2mp_fuelgauge.c, or s2mp_regulator.c. These files contain critical information:
- I2C/SPI Addresses: Often defined as macros or within device tree entries (DTS/DSI files). Look for structures initializing I2C devices.
- Register Definitions: Enumerations or macros defining register addresses (e.g., S2MP_REG_CHG_CTRL0, S2MP_REG_BAT_OCV).
- Read/Write Functions: Functions like s2mp_i2c_read and s2mp_i2c_write abstract the bus communication. Analyzing how these functions are used with specific register addresses reveals their purpose.
Example: Extracting I2C Address from Device Tree

In a device tree source (DTS) file (e.g., arch/arm/boot/dts/exynos9820-gts.dtsi for a Galaxy S10), you might find a node similar to this:
```
&i2c1 {    status =
```
May 29, 2026
From Zero to Secure World Shell: Exploiting a TrustZone TA Logic Bug Step-by-Step Introduction to the Secure World and TrustZone The Android ecosystem relies heavily on security features, and at its core lies ARM TrustZone – a hardware-backed security extension that partitions a system’s resources into a ‘Normal World’ and a ‘Secure World’. The Normal World runs the rich operating system (like Android), while the Secure World hosts Trusted Applications (TAs) that handle sensitive operations such as key management, biometric authentication, and digital rights management (DRM). This isolation is critical; a compromise in the Normal World should not directly affect the Secure World. However, vulnerabilities can still exist within the Trusted Applications themselves, often due to subtle logic flaws or improper state management. This article will walk through a hypothetical, yet realistic, scenario of exploiting such a logic bug in a TrustZone TA to ultimately achieve a ‘Secure World Shell’ – arbitrary code execution within the Secure Environment. Understanding ARM TrustZone Architecture ARM TrustZone creates two execution environments: the Normal World (NW) and the Secure World (SW). A monitor mode facilitates the secure transition between these two worlds. Trusted Applications (TAs) run within the Secure World, often managed by a Trusted Execution Environment (TEE) OS like OP-TEE or Trusty. Communication between the NW and SW happens via a TEE Client API, where applications in the NW can invoke commands in specific TAs. Normal World (NW): Runs Android, user applications, and standard operating system components. Secure World (SW): Runs a minimal TEE OS and trusted applications. Designed for high-security operations. Monitor Mode: A special CPU mode that acts as a gatekeeper, mediating transitions between NW and SW. Trusted Applications (TAs): Small, specialized programs residing in the SW, performing sensitive tasks. Identifying a Vulnerable Trusted Application Our journey begins with identifying a target TA. In a real-world scenario, this involves reverse engineering firmware images to extract TAs, then statically analyzing them using tools like Ghidra or IDA Pro. We’d look for patterns like: Complex state machines. Input validation flaws (though we’re focusing on logic here). Improper sequence of operations. Insufficient authentication or authorization checks at critical junctures. For this tutorial, let’s assume we’ve identified a `KeyManagerTA` responsible for provisioning and managing cryptographic keys. This TA exposes several commands, including `CMD_PROVISION_KEY` and `CMD_SET_INITIALIZED_FLAG`. Hypothetical Vulnerability: KeyManagerTA State Confusion Our `KeyManagerTA` is designed such that a ‘master key’ can only be provisioned once, during initial device setup. Subsequent key provisioning for user-specific keys requires authentication based on the already-provisioned master key. The logic error lies in the sequence check: The TA maintains an internal state variable, `is_provisioned`, which is set to `true` only after `CMD_SET_INITIALIZED_FLAG` is called. The `CMD_PROVISION_KEY` function has a critical flaw: it checks if `is_provisioned` is `true` *before* enforcing strict authentication for the `MASTER_KEY_ID`. If `is_provisioned` is `false`, it assumes it’s the initial setup and allows `MASTER_KEY_ID` provisioning without sufficient authentication, *even if other keys have already been provisioned* through the same command. The sequence intended by the developer: `CMD_PROVISION_KEY(MASTER_KEY_ID, original_master_key)` (only once, highly secured). `CMD_SET_INITIALIZED_FLAG()`. `CMD_PROVISION_KEY(USER_KEY_ID, user_key)` (requires `MASTER_KEY` authentication). The actual vulnerable logic: // Inside KeyManagerTA's CMD_PROVISION_KEY handler logic:if (!is_provisioned) { // Initial provisioning phase. // Critical bug: Authentication for MASTER_KEY_ID is bypassed here // if is_provisioned is false, regardless of prior non-master key provisions. if (key_id == MASTER_KEY_ID) { // Allow provisioning master key without full auth. // This is the flaw if we can reach here after non-master keys. store_key(key_id, key_data); return TEE_SUCCESS; } else { // Allow provisioning other keys, assume initial setup for other keys. store_key(key_id, key_data); return TEE_SUCCESS; }} else { // Device is provisioned. All key provisioning requires master key auth. // ... (authenticate using current master key) // ...} Crafting the Exploit Primitive: Bypassing Master Key Authentication Our goal is to provision our own `MASTER_KEY`. Using the identified logic bug, we can achieve this with a specific sequence of calls from the Normal World. We’ll use the GlobalPlatform TEE Client API to interact with the TA. Step 1: Locate the TA and its UUID First, we need to find the UUID of our `KeyManagerTA`. This can be found by examining the TA files (e.g., `.ta` files on disk, or embedded in firmware). Let’s assume the UUID is `12345678-1234-1234-1234-1234567890AB`. $ adb shell find /vendor /system -name "*.ta"# Example output:/vendor/lib/tee/12345678-1234-1234-1234-1234567890AB.ta Step 2: Connect to the TEE and Open a Session Using a custom Normal World application (or a modified `tee_client_app`), we initiate communication. #include <tee_client_api.h>#include <stdio.h>#include <string.h>TEEC_Context ctx;TEEC_Session sess;TEEC_UUID uuid = { 0x12345678, 0x1234, 0x1234, { 0x12, 0x34, 0x12, 0x34, 0x56, 0x78, 0x90, 0xAB } };TEEC_Result res;void connect_ta() { res = TEEC_InitializeContext(NULL, &ctx); if (res != TEEC_SUCCESS) { printf("TEEC_InitializeContext failed with code 0x%x ", res); return; } res = TEEC_OpenSession(&ctx, &sess, &uuid, TEEC_LOGIN_PUBLIC, NULL, NULL, NULL); if (res != TEEC_SUCCESS) { printf("TEEC_OpenSession failed with code 0x%x ", res); TEEC_FinalizeContext(&ctx); return; } printf("Session opened successfully! ");} Step 3: Trigger the Logic Bug – Provisional Key Provisioning We’ll first provision a dummy, non-master key. This call succeeds because `is_provisioned` is initially `false`. Crucially, this step does *not* set `is_provisioned` to `true`, as that’s handled by `CMD_SET_INITIALIZED_FLAG`. #define CMD_PROVISION_KEY 1#define USER_KEY_ID_1 0x1000#define MASTER_KEY_ID 0x0001void provision_dummy_key() { TEEC_Operation op; uint8_t dummy_key[16] = {0xAA, 0xBB, 0xCC, 0xDD, 0xEE, 0xFF, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99}; memset(&op, 0, sizeof(op)); op.paramTypes = TEEC_PARAM_TYPES(TEEC_VALUE_INPUT, TEEC_MEMREF_TEMP_INPUT, TEEC_NONE, TEEC_NONE); op.params[0].value.a = USER_KEY_ID_1; // Our non-master key ID op.params[1].memref.buffer = dummy_key; op.params[1].memref.size = sizeof(dummy_key); printf("Attempting to provision dummy key (USER_KEY_ID_1)... "); res = TEEC_InvokeCommand(&sess, CMD_PROVISION_KEY, &op, NULL); if (res != TEEC_SUCCESS) { printf("Dummy key provisioning failed with code 0x%x ", res); } else { printf("Dummy key provisioned successfully. is_provisioned is still false. "); }} Step 4: Exploit the Logic Bug – Master Key Overwrite Now, while `is_provisioned` is still `false`, we immediately attempt to provision our *attacker-controlled master key* using `MASTER_KEY_ID`. Due to the logic flaw, the TA treats this as an May 29, 2026
Bypassing TrustZone Mitigations: Defeating PXN, ROX, and Other Secure World Protections Introduction to ARM TrustZone and Secure World Exploitation ARM TrustZone technology is a critical security extension integrated into modern ARM processors, providing a hardware-enforced isolation mechanism that creates two distinct execution environments: the Normal World and the Secure World. In Android devices, the Secure World typically hosts a Trusted Execution Environment (TEE) that runs sensitive applications like DRM, mobile payments, and biometric authentication, isolated from the potentially compromised Normal World (where Android OS runs). While TrustZone significantly enhances security, vulnerabilities in its implementation or in Trusted Applications (TAs) can allow an attacker to gain control within the Secure World, undermining the root of trust. Exploiting the Secure World is a formidable challenge, primarily due to a suite of hardware-backed mitigations designed to prevent arbitrary code execution and memory manipulation. Among these, Privileged Execute-Never (PXN) and Read-Only eXecute (ROX) are fundamental in preventing traditional exploit techniques. This article delves into these mitigations and explores advanced strategies for bypassing them, paving the way for full Secure World compromise. Understanding TrustZone’s Dual World Architecture Before diving into bypass techniques, it’s crucial to grasp the architectural fundamentals of TrustZone: Normal World (Non-secure): This is where the rich operating system (e.g., Android) and user applications execute. Its access to hardware resources is mediated by the Secure World. Secure World (Trusted): This isolated environment runs a minimal, security-focused OS (e.g., OP-TEE, Trusty) and Trusted Applications. It has full access to system resources and can control access for the Normal World. Secure Monitor Call (SMC): The only entry point from the Normal World into the Secure World. It’s used for controlled transitions and requesting services from the TEE. EL3 (Exception Level 3): The highest privilege level, typically running the Secure Monitor, responsible for switching between Normal and Secure worlds. The isolation is enforced by hardware mechanisms, including a dedicated Memory Management Unit (MMU) for the Secure World, which enforces strict memory access rules. Core TrustZone Mitigations: PXN and ROX PXN and ROX are crucial hardware features that harden the Secure World against common exploit techniques: Privileged Execute-Never (PXN) PXN is an ARMv8-A architecture feature that prevents privileged execution from data pages. In the context of the Secure World, this means that even if an attacker achieves kernel-level control (e.g., at EL1 or EL0 within the Secure World), they cannot simply inject shellcode into a data buffer and execute it. The MMU will prevent code execution from any page marked as data, irrespective of privilege level. Read-Only eXecute (ROX) ROX, or Write-eXecute-Never (WXN) as it’s sometimes called in certain contexts, is a broader policy often enforced by the Secure World kernel or bootloader. It mandates that memory pages cannot be both writable and executable simultaneously. Code pages are typically marked as read-only and executable, while data pages are writable but non-executable. This strictly separates code and data, preventing an attacker from writing new code into an executable region or modifying existing code in a writable region that could then be executed. Bypassing PXN: Reaching for ROP in the Secure World Since PXN prevents direct code injection and execution from data pages, attackers must rely on existing code within the Secure World to achieve arbitrary execution. This typically involves Return-Oriented Programming (ROP). The ROP Paradigm in the Secure World ROP involves chaining together small sequences of existing instructions (gadgets) found in the Secure World’s executable memory. Each gadget typically ends with a return instruction (e.g., RET), allowing control to pass to the next gadget on the stack. To achieve ROP, an attacker needs: An arbitrary write primitive: To overwrite a return address on the stack or a function pointer in memory. Information disclosure: To leak the base address of Secure World images (kernel, TAs) and find suitable gadgets. Gadgets: Short instruction sequences that perform desired operations (e.g., modifying registers, memory reads/writes, calling functions). A typical ROP chain might look like this (pseudo-assembly): // Example ROP Gadget 1: Pop R0, Pop PC (return) -> sets argument for next call ADD R0, SP, #0x10 // Load a value from stack into R0LDR LR, [SP, #0x4] // Load next return addressADD SP, SP, #0x8RET // Branch to LR (next gadget) // Example ROP Gadget 2: Call an arbitrary functionLDR R1, [SP, #0x4] // Load argumentBLX R0 // Call function pointer in R0LDR LR, [SP]ADD SP, SP, #0x4RET // ... and so on, to construct a desired payload. The challenge lies in finding enough useful gadgets within the usually smaller and more specialized Secure World binaries, which might be compiled with fewer shared libraries than a full OS. Bypassing ROX: Memory Remapping and Privilege Escalation ROX presents a more fundamental challenge as it prevents any single memory page from being simultaneously writable and executable. Bypassing ROX often requires exploiting vulnerabilities that allow for memory permission changes or for mapping new memory with custom permissions. Exploiting Memory Management Vulnerabilities The most direct way to bypass ROX is to exploit a vulnerability within the Secure World kernel’s memory management unit (MMU) routines. If an attacker can achieve privilege escalation within the Secure World (e.g., from a TA’s EL0 to Secure EL1 kernel), they might gain the ability to manipulate page table entries (PTEs) directly. Consider a hypothetical vulnerability where a Secure EL1 driver has a bug in how it handles memory region requests from a TA, allowing the TA to request a mapping with arbitrary permissions. An attacker could then map a new page as both writable and executable: // Hypothetical Secure World Kernel MMU function (simplified)int map_memory_region(uint64_t vaddr, uint64_t paddr, size_t size, uint32_t permissions) { // ... validation logic (vulnerable if permissions are not strictly checked) pte_t *pte = get_pte_for_vaddr(vaddr); if (!pte) { // Create new page table entry pte = create_new_pte(vaddr, paddr, size); } update_pte_permissions(pte, permissions); // Vulnerability here if permissions can be controlled // ... return 0;} // Attacker's goal (from compromised TA/Secure EL1)uint32_t WX_PERMISSIONS = MMU_FLAG_READ | MMU_FLAG_WRITE | MMU_FLAG_EXECUTE_EL0 | MMU_FLAG_EXECUTE_EL1;map_memory_region(attacker_vaddr, attacker_paddr, PAGE_SIZE, WX_PERMISSIONS); If such a vulnerability exists, the attacker could map a new memory page with WX permissions, write their shellcode into it, and then execute it, completely bypassing PXN and ROX. This is highly privileged and challenging to achieve but represents a complete compromise. Leveraging Existing WX Regions (Rare) In some rare or legacy Secure World implementations, there might be small, legitimate regions of memory that are marked as both writable and executable. These are usually for very specific purposes, such as JIT compilers or highly specialized bootloader stages. Discovering and exploiting such regions is a high-value target for code injection. Putting it Together: A Conceptual Exploitation Flow A successful Secure World exploit bypassing PXN and ROX might follow these steps: Initial Vulnerability Identification: Discover a bug in a Trusted Application (TA) or the Secure World kernel. This could be a buffer overflow, integer overflow, use-after-free, or a logical flaw. Achieve Arbitrary Read/Write Primitive: Leverage the initial vulnerability to gain the ability to read and write arbitrary memory locations within the Secure World. This is a critical prerequisite for most advanced exploitation. Information Disclosure (Secure World ASLR Bypass): Use the arbitrary read primitive to leak Secure World memory, revealing the base addresses of the Secure OS kernel and TAs. This is essential for finding ROP gadgets and understanding the memory layout (bypassing ASLR). ROP Chain Construction (PXN Bypass): If direct WX memory is not attainable, use the leaked memory to find suitable ROP gadgets. Construct a ROP chain that aims to either: Perform the desired malicious actions using existing code. Or, more powerfully, locate and call a Secure World kernel function that can modify MMU page table entries. MMU Page Table Manipulation (ROX Bypass): If the ROP chain or a direct vulnerability allows calling a privileged MMU function, modify a page table entry to mark a data page (where the attacker can write) as executable. Alternatively, map a new page with both write and execute permissions. Shellcode Injection and Execution: Once a writable and executable memory region is established (either by remapping or using a rare existing one), inject custom shellcode into it and transfer execution to that shellcode. This grants full control over the Secure World. Challenges and Future Outlook Exploiting ARM TrustZone and bypassing mitigations like PXN and ROX is an extremely complex undertaking. Challenges include: Lack of Debugging Tools: Traditional debugging tools are often unavailable or disabled in the Secure World, making analysis difficult. Vendor-Specific Implementations: TrustZone implementations vary significantly between SoC vendors (Qualcomm, Samsung, MediaTek), requiring deep, target-specific reverse engineering. Code Obfuscation: Secure World firmware often employs heavy obfuscation to deter analysis. Hardware-Level Security Extensions: Newer ARM features like Memory Tagging Extension (MTE) and Pointer Authentication Codes (PAC) further complicate exploitation by protecting against memory corruption and ROP/JOP attacks. As hardware security continually evolves, attackers must develop increasingly sophisticated techniques to overcome these robust protections. Understanding the underlying hardware mechanisms and the intended purpose of each mitigation is paramount for any successful bypass strategy. May 29, 2026
Troubleshooting Android Power Issues: A PMIC Register Modification Script for Diagnosis Introduction: The Heart of Android Power Management Android devices, despite their sophistication, are frequently plagued by power-related issues: sudden shutdowns, incessant boot loops, rapid battery drain, or failure to charge. At the core of these problems often lies the Power Management Integrated Circuit (PMIC). The PMIC is a critical component responsible for regulating power flow across the entire device, managing battery charging, power sequencing for various subsystems (CPU, GPU, memory, peripherals), and thermal protection. Understanding and, more importantly, inspecting its operational state can be the key to diagnosing elusive power issues that software logs alone cannot reveal. Understanding the PMIC and Its Role A PMIC is a complex system-on-chip that integrates multiple voltage regulators (LDOs, SMPS), battery chargers, power-on reset generators, and various protection circuits. Modern Android devices often use PMICs from manufacturers like Qualcomm (e.g., PM89XX, PM660L series), MediaTek, or Samsung. These PMICs expose a myriad of internal registers that control their behavior and report their status. By reading these registers, engineers can gain deep insights into voltage levels, current draw, charging status, thermal conditions, and the health of individual power rails. Common power-related symptoms that point to a PMIC issue include: Device not powering on. Random reboots or shutdowns. Battery not charging or charging excessively slowly. Device overheating without significant load. Incorrect battery percentage readings. While software debugging tools (like `dumpsys batterystats`) provide high-level insights, they often abstract away the granular hardware-level details accessible directly from PMIC registers. This is where direct register manipulation becomes invaluable for advanced diagnostics. Prerequisites for PMIC Register Diagnosis Before diving into register manipulation, ensure you have the following: Rooted Android Device: Direct memory access tools like `devmem2` require root privileges. ADB Access: Android Debug Bridge is essential for interacting with the device shell. `devmem2` or Similar Tool: A utility to read/write specific memory addresses. If `devmem2` is not pre-installed or easily available, you might need to compile it for your device’s architecture or use a kernel module that provides similar functionality. Kernel Source/Device Tree (DTB) Knowledge (Recommended): Knowing where to find PMIC definitions in your device’s kernel source or device tree blob is crucial for identifying correct base addresses and register offsets. Datasheets for the specific PMIC can also provide this information. Locating PMIC Register Addresses PMIC registers are memory-mapped, meaning they appear at specific physical memory addresses. These addresses are hardware-dependent. For Qualcomm-based platforms, PMIC registers are often mapped into a dedicated address space accessible via an SPMI (System Power Management Interface) controller. The base address for the PMIC’s register space is typically defined in the device’s kernel source code, specifically within the device tree files (e.g., `.dtsi` or `.dts` files under `arch/arm64/boot/dts/qcom/`). Look for nodes related to May 29, 2026
Deep Dive: Reverse Engineering PMIC Architectures on Qualcomm Snapdragon SoCs Introduction: Unlocking the Power Beneath Power Management Integrated Circuits (PMICs) are the unsung heroes of modern electronics, orchestrating the complex power delivery systems within a device. On Qualcomm Snapdragon Systems-on-Chip (SoCs), PMICs are particularly sophisticated, often integrating multiple power rails, battery charging, thermal management, and various peripheral controls. For advanced Android hardware reverse engineers, understanding and manipulating PMIC registers opens doors to custom power optimizations, feature enablement, or even debugging obscure hardware issues. This article delves into the intricacies of reverse engineering Qualcomm PMIC architectures, focusing on practical approaches to identify and interact with their registers. Qualcomm’s PMIC Architecture Overview Qualcomm’s Snapdragon platforms typically utilize dedicated PMIC chips, often from their own SMB (Snapdragon Power Management) series or highly integrated PM (Power Management) series. These PMICs communicate with the main SoC primarily via the System Power Management Interface (SPMI). While older or auxiliary power management components might still use I2C, SPMI is the dominant bus for the core PMIC on modern Snapdragon SoCs, offering higher efficiency and reliability. The Role of SPMI SPMI is a low-pin-count, two-wire serial bus designed specifically for power management. It’s more complex than I2C, supporting multiple masters and slaves, and offering features like power management requests (PMR) and bus arbitration. This complexity makes direct userspace manipulation challenging without kernel support. Identifying the PMIC and Its Configuration The first step in reverse engineering is identification. Since public datasheets for Qualcomm PMICs are rare, we often rely on analyzing the Android kernel source code, specifically the Device Tree (DT) and relevant drivers. Device Tree Analysis The Device Tree (found in files like .dts and .dtsi within the kernel source’s arch/arm64/boot/dts/qcom/ directory) describes the hardware configuration. PMIC nodes are typically defined under the SPMI bus controller. Look for entries like qcom,spmi-pmic or specific PMIC chip identifiers. // Example snippet from a Snapdragon Device Tree (.dtsi) file:qcom,spmi-controller@c000000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc000000 0x10000>; interrupts = <0 144 0>, <0 145 0>, <0 146 0>, <0 147 0>; #address-cells = <2>; #size-cells = <0>; qcom,num-peripherals = <16>; qcom,channel-map = <0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 9 9 10 10 11 11 12 12 13 13 14 14 15 15>; pmic@0 { compatible = "qcom,pm8150"; // Example PMIC model reg = <0x0 0x0>; // ... various PMIC sub-nodes for regulators, GPIOs, etc. }; pmic@1 { compatible = "qcom,pm8150b"; // Another PMIC instance or companion chip reg = <0x1 0x0>; // ... };}; In this example, pmic@0 and pmic@1 represent different PMIC instances or logical PMICs on the SPMI bus, identified by their slave ID (0x0 and 0x1 respectively) and compatible strings (e.g., qcom,pm8150). Kernel Driver Discovery and Runtime Information Once you have identified the PMIC model, explore the kernel source for corresponding drivers: drivers/spmi/: Contains the core SPMI bus driver. drivers/regulator/: PMIC regulators are often managed by the generic Linux regulator framework. Look for Qualcomm-specific drivers like qcom_pmic_glink.c or qcom_spmi_regulator.c. drivers/power/supply/: For battery charging and power supply status, drivers often interface with the PMIC. On a rooted Android device, you can inspect the `/sys/bus/spmi/devices/` directory to see the active SPMI peripherals: adb shellsu -c "ls /sys/bus/spmi/devices/" You might see entries like `spmi-0:00`, `spmi-0:01`, corresponding to the SPMI controller and slave IDs found in the Device Tree. Understanding PMIC Registers The May 29, 2026
Building Your Own Malicious TrustZone Application: A PoC for Android Secure World Control Introduction to ARM TrustZone and Secure World Control ARM TrustZone technology is a critical security extension integrated into modern ARM processors, providing a hardware-isolated execution environment known as the Secure World. This Secure World operates alongside the Normal World (where Android runs) to protect sensitive data and operations, such as cryptographic keys, digital rights management (DRM) content, and biometric authentication. TrustZone achieves this by partitioning system resources, allowing only trusted applications (TAs) within a Trusted OS (T-OS) to access secure memory and peripherals. This article details the theoretical and practical steps involved in developing a Proof-of-Concept (PoC) malicious Trusted Application. Our goal is to illustrate the immense power and potential dangers of controlling the Secure World by demonstrating how an unsigned, custom TA could be designed to log sensitive operations or extract protected data, given the capability to load it onto a device. This is purely for educational and research purposes, highlighting the importance of secure boot and firmware integrity checks in preventing such attacks on real-world devices. Prerequisites and Threat Model Essential Tools and Knowledge A development board or a rooted Android device with an unlocked bootloader, allowing custom kernel/firmware flashing. Examples include devices supporting OP-TEE. Familiarity with ARM architecture, assembly language, and C programming. Understanding of Linux kernel module development and Android’s native development kit (NDK). A cross-compilation toolchain for ARM (e.g., arm-linux-gnueabihf-). A TEE SDK (e.g., OP-TEE Client/Trusted OS development kit). The Malicious TA Threat Model In a real-world scenario, devices employ secure boot mechanisms that verify the cryptographic signatures of all boot components, including the Trusted OS and its Trusted Applications. Our PoC assumes a scenario where these checks are either bypassed (e.g., through a bootloader exploit) or deliberately disabled in a research environment, allowing an unsigned TA to be loaded. The ‘malicious’ aspect of our TA will be its ability to access resources or perform actions typically restricted to legitimate, signed TAs, such as logging secure data flows or attempting to modify secure configurations. Understanding TrustZone Architecture and OP-TEE TrustZone divides the system into two virtual processors: the Normal World (NW) for general-purpose OS like Android, and the Secure World (SW) for the Trusted OS. Communication between NW and SW occurs via Secure Monitor Calls (SMCs). The Trusted OS (e.g., OP-TEE, Trusty) manages Trusted Applications (TAs), which are isolated binaries executed within the SW. Our PoC will involve creating a custom TA for the Secure World and a client application (CA) in the Normal World to interact with it. OP-TEE High-Level Interaction Trusted Application (TA): Runs in Secure World, performs secure operations. Client Application (CA): Runs in Normal World (Android), requests services from TA. TEE Client API: Standardized API (e.g., GlobalPlatform TEE Client API) used by CA to communicate with the T-OS. Secure Monitor: Handles context switching between NW and SW. Developing the Malicious Trusted Application (TA) We’ll create a simple OP-TEE TA that, for demonstration, logs a secret string every time it’s invoked and potentially tries to read a dummy May 29, 2026
Practical TrustZone Memory Corruption: Heap Overflows and UaF in Trusted Applications Introduction to TrustZone Security and Vulnerabilities ARM TrustZone technology partitions a system into two distinct environments: a Normal World and a Secure World. The Normal World typically runs a rich operating system like Android or Linux, while the Secure World hosts a Trusted Execution Environment (TEE) that executes sensitive operations, often involving cryptographic keys, biometric data, or Digital Rights Management (DRM). Trusted Applications (TAs) run within this Secure World, benefiting from its hardware-enforced isolation and protection. While TrustZone significantly enhances device security, the Trusted Applications themselves are not immune to software vulnerabilities. Memory corruption flaws, such as heap overflows and Use-after-Free (UaF), pose significant threats. Exploiting these can lead to privilege escalation within the TEE, allowing an attacker to bypass security features, compromise sensitive data, or even gain control over the Secure World, effectively undermining the entire TrustZone security model. This article delves into the practical aspects of identifying and exploiting heap overflows and UaF vulnerabilities in Trusted Applications. TrustZone Architecture and Trusted Applications Overview The ARM TrustZone mechanism leverages a hardware feature that allows the processor to switch between two states: Secure and Non-secure. This context switch is managed by the Monitor Mode, which is entered via a Secure Monitor Call (SMC) instruction. Applications in the Normal World communicate with TAs in the Secure World using an API provided by the TEE Operating System (TEE OS), often following the GlobalPlatform TEE Client API specification. Trusted Applications are essentially user-mode programs within the Secure World. They are loaded and executed by the TEE OS and have access to secure memory regions and specific hardware peripherals. Unlike normal user-space applications, TAs operate with a smaller, more specialized runtime environment, often employing custom memory allocators and limited standard library functions, making their heap management behavior critical to understand for security analysis. Memory Management in Trusted Applications Memory management within TAs is crucial for understanding memory corruption. TEE OS implementations (like OP-TEE, Trusty TEE) provide their own heap allocators for TAs. These allocators, while often simpler than those in rich operating systems (e.g., glibc’s ptmalloc), are still susceptible to the same fundamental vulnerabilities if not implemented carefully. The core principles of heap management – allocating chunks of memory and managing metadata (chunk size, status bits) – remain consistent. /* Simplified TA Heap Allocation Example (Conceptual) */#include <tee_internal_api.h>void* my_ta_alloc(size_t size) { // In a real TA, this would call TEE_Malloc or a custom allocator void* ptr = TEE_Malloc(size); if (ptr == NULL) { EMSG( May 29, 2026
Anatomy of a TrustZone Exploit: Dissecting Real-World CVEs on Popular Android SoCs Introduction to ARM TrustZone and Secure Computing The ARM TrustZone technology is a hardware-enforced security extension integral to modern System-on-Chips (SoCs), particularly prevalent in Android devices. It partitions a single physical core into two virtual realms: the Normal World and the Secure World. This architecture is fundamental for protecting sensitive operations such as cryptographic key management, DRM content playback, and biometric authentication from the potentially compromised Normal World (where the Android OS and applications run). Understanding its architecture and common vulnerabilities is crucial for advanced security research and exploit development. This article dives into the anatomy of TrustZone exploits, exploring the underlying principles, common attack surfaces, and a simplified real-world exploitation scenario. Our focus will be on the Secure World components, primarily Trusted Applications (TAs) and the Secure Monitor, which serve as the gatekeepers between the two worlds. TrustZone Fundamentals: Secure vs. Normal Worlds At the heart of TrustZone lies the concept of isolation. The processor can be in one of two states: Secure or Non-Secure. Context switching between these states is managed by the Secure Monitor, typically running at EL3 (Exception Level 3), the highest privilege level. When a Normal World component needs a secure service, it initiates a Secure Monitor Call (SMC) instruction. This traps into the Secure Monitor, which then validates the request and dispatches it to the appropriate Secure World handler, often a Trusted Application. Normal World (EL0, EL1): Runs the Android OS, user applications, and untrusted drivers. Limited access to system resources. Secure World (EL0, EL1): Runs Trusted Applications (TAs), secure OS components (like Trusty OS or OP-TEE), and secure drivers. Has access to protected memory, peripherals, and cryptographic hardware. Secure Monitor (EL3/EL2): Acts as a gatekeeper, mediating transitions between the Normal and Secure Worlds via SMCs. Verifies requests and ensures proper context switching. Trusted Applications are the primary interface for Normal World services into the Secure World. They implement specific security functions and run within a Trusted Execution Environment (TEE) operating system (e.g., Trusty, OP-TEE, QSEE). These TAs expose a set of entry points that can be invoked from the Normal World using a client application and the TEE driver. Common TrustZone Attack Surfaces Exploiting TrustZone often involves finding vulnerabilities in the software running within the Secure World. The primary attack surfaces include: Trusted Applications (TAs): These are the most common targets. TAs process input directly from the Normal World, making them susceptible to typical software vulnerabilities like buffer overflows, integer overflows, format string bugs, and race conditions. A successful exploit here can lead to arbitrary code execution within the TEE, allowing an attacker to steal keys, bypass DRM, or escalate privileges within the Secure World. Secure Monitor Call (SMC) Handlers: The Secure Monitor (EL3/EL2) is critical for system integrity. Vulnerabilities in its SMC handlers, which process requests from both worlds, are extremely severe. Exploiting an EL3 vulnerability could grant an attacker complete control over the SoC, potentially bypassing all hardware-enforced security. Secure World Drivers/Services: Similar to TAs, other secure drivers or services within the TEE can have vulnerabilities. Inter-Processor Communication (IPC) Mechanisms: The communication channels between the Normal and Secure Worlds, or even between different Secure World components, can expose vulnerabilities if not properly secured (e.g., shared memory regions, message queues). Dissecting a Hypothetical CVE: Trusted Application Buffer Overflow Let’s consider a common vulnerability type: a buffer overflow within a Trusted Application. This scenario often arises when a TA copies user-supplied data from the Normal World into a fixed-size buffer in the Secure World without adequate length checks. Vulnerability Discovery Discovery often begins with reverse engineering the TEE framework and available TAs. Tools like Ghidra or IDA Pro are indispensable for disassembling the TA binaries (typically ELF files). Researchers look for functions that handle Normal World input, paying close attention to memory copy operations (`memcpy`, `strcpy`, `read_from_ns_buffer`) and their associated size parameters. For example, a TA might have a function that processes a command block sent from the Normal World client: // Hypothetical vulnerable TA function in C (Secure World)void handle_command(uint32_t cmd_id, void* input_buffer, size_t input_len) { char local_buffer[256]; if (cmd_id == SOME_VULNERABLE_CMD) { // Simulate copying data from Normal World // VULNERABLE: No length check against local_buffer size if (input_len > 0 && input_buffer != NULL) { memcpy(local_buffer, input_buffer, input_len); // Potential overflow } // ... further processing with local_buffer ... }} The Normal World client would typically allocate a buffer, populate it, and then call an API function provided by the TEE client library to send this buffer to the TA. The `input_len` parameter, controlled by the Normal World, is critical here. Exploitation Steps Assuming we’ve identified the vulnerable `memcpy` and can control `input_len` from the Normal World, the exploitation steps might look like this: Craft Malicious Input: From the Normal World, we create a payload (`input_buffer`) larger than `local_buffer`’s capacity (256 bytes) and set `input_len` to our oversized payload length. The payload would typically contain ROP (Return-Oriented Programming) gadgets. Trigger Overflow: We invoke the `SOME_VULNERABLE_CMD` through the TEE client API. The Normal World client application prepares the malicious input and calls the TEE communication function. Control PC/LR: When `memcpy` is called with the oversized `input_len`, it overwrites the stack, including the return address (Link Register or LR) for the `handle_command` function. By placing the address of our first ROP gadget at the overwritten LR location, we gain control over the program counter (PC) upon function return. ROP Chain Execution: With PC control, we can execute a ROP chain. Gadgets would be extracted from the TA’s binary itself or the TEE OS libraries. A typical goal might be to call a sensitive function, read/write protected memory, or potentially even escalate to a higher privilege level within the TEE if further vulnerabilities exist or by manipulating TA internal state. Example Normal World Client (simplified pseudo-code): // Normal World Client (Android App/Driver)int main() { tee_session_handle_t session = open_tee_session(&TA_UUID); char payload[500]; // Our malicious oversized buffer memset(payload, 'A', sizeof(payload)); // Place ROP gadget addresses within payload // ... payload[256] = ROP_GADGET_1_ADDR; ... // ... payload[260] = ROP_GADGET_2_ADDR; ... send_command_to_ta(session, SOME_VULNERABLE_CMD, payload, sizeof(payload)); close_tee_session(session); return 0;} The `send_command_to_ta` function would internally map the payload to a shared memory buffer and trigger an SMC, which then gets routed to the TA. This precise control over `input_len` from the Normal World is the key to triggering the buffer overflow. Post-Exploitation Goals Once arbitrary code execution is achieved within the TA, the attacker can: Extract DRM keys or other sensitive data from Secure World memory. Manipulate secure cryptographic operations. Further exploit the TEE OS itself to gain higher privileges or break isolation between TAs. Potentially pivot to compromise the Secure Monitor (EL3) if a subsequent vulnerability is found there, leading to a full platform compromise. Mitigation and Defense Defending against TrustZone exploits requires a multi-layered approach: Secure Coding Practices: Strict input validation, bounds checking, and use of safe memory manipulation functions are paramount for TA developers. Static and Dynamic Analysis: Regular security audits, static code analysis (SAST), and fuzzing of TAs and SMC handlers are essential to identify vulnerabilities early. Memory Protections: Implementing ASLR (Address Space Layout Randomization) and DEP (Data Execution Prevention) within the TEE makes exploitation harder, although often less effective than in the Normal World due to smaller codebases and less entropy. Least Privilege: TAs should operate with the minimum necessary privileges and only access specific memory regions required for their function. Regular Updates: Prompt patching of identified CVEs by SoC vendors and device manufacturers is crucial. Conclusion The ARM TrustZone architecture provides a powerful foundation for secure computing on Android devices, but like any complex system, it is not impervious to attack. Exploiting TrustZone often involves meticulous reverse engineering and understanding the intricate interactions between the Normal and Secure Worlds. By dissecting a hypothetical buffer overflow in a Trusted Application, we’ve demonstrated the typical flow from vulnerability discovery to achieving arbitrary code execution within the TEE. As the reliance on hardware-backed security grows, so too does the importance of continuous research into securing these critical components against sophisticated adversaries. May 29, 2026


	
	
		
	
	
	
	
		
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Author: admin

Introduction to Power Management ICs (PMICs) in Android Systems

Understanding PMIC Architecture and Kernel Interaction

The Role of PMICs

The Linux Kernel’s Regulator Framework

Identifying Your Device’s PMIC and Drivers

1. Physical Inspection & Schematics (If Available)

2. Kernel Logs (dmesg)

3. Device Tree Blob (DTB) Analysis

Interacting with PMIC Regulators via sysfs

Listing Regulators

Reading Regulator Status

Adjusting Regulator Voltage (CAUTION!)

Direct PMIC Register Access (Advanced and Highly Risky)

Method: Custom Kernel Module for I2C/SPI Access

Practical Use Cases and Safety Considerations

Use Cases:

Safety and Precautions:

Conclusion

Introduction to PMIC Manipulation

What is a PMIC?

Prerequisites for PMIC Hacking

Identifying Your Device’s PMIC

Software-Based PMIC Register Access (I2C-dev)

Locating the I2C Bus

Using i2c-tools

Detecting PMIC Address

Reading a PMIC Register

Writing to a PMIC Register

Hardware-Based PMIC Register Access (Advanced Techniques)

The Need for Hardware Access

Snooping I2C Communication with a Logic Analyzer

Direct I2C Control via JTAG/SWD Debugger

Practical Applications and Use Cases

Risks and Ethical Considerations

Conclusion

Introduction: Unlocking Power Beyond Android’s Default

Phase 1: Identifying the PMIC and Initial Reconnaissance

Physical Inspection and Chip Identification

The PMIC’s Communication Bus

Phase 2: Software-Based PMIC Interaction Discovery

Kernel Source Analysis: Unveiling the Drivers

Introduction to the Secure World and TrustZone

Understanding ARM TrustZone Architecture

Identifying a Vulnerable Trusted Application

Hypothetical Vulnerability: KeyManagerTA State Confusion

Crafting the Exploit Primitive: Bypassing Master Key Authentication

Step 1: Locate the TA and its UUID

Step 2: Connect to the TEE and Open a Session

Step 3: Trigger the Logic Bug – Provisional Key Provisioning

Step 4: Exploit the Logic Bug – Master Key Overwrite

Introduction to ARM TrustZone and Secure World Exploitation

Understanding TrustZone’s Dual World Architecture

Core TrustZone Mitigations: PXN and ROX

Privileged Execute-Never (PXN)

Read-Only eXecute (ROX)

Bypassing PXN: Reaching for ROP in the Secure World

The ROP Paradigm in the Secure World

Bypassing ROX: Memory Remapping and Privilege Escalation

Exploiting Memory Management Vulnerabilities

Leveraging Existing WX Regions (Rare)

Putting it Together: A Conceptual Exploitation Flow

Challenges and Future Outlook

Introduction: The Heart of Android Power Management

Understanding the PMIC and Its Role

Prerequisites for PMIC Register Diagnosis

Locating PMIC Register Addresses

Introduction: Unlocking the Power Beneath

Qualcomm’s PMIC Architecture Overview

The Role of SPMI

Identifying the PMIC and Its Configuration

Device Tree Analysis

Kernel Driver Discovery and Runtime Information

Understanding PMIC Registers

Introduction to ARM TrustZone and Secure World Control

Prerequisites and Threat Model

Essential Tools and Knowledge

The Malicious TA Threat Model

Understanding TrustZone Architecture and OP-TEE

OP-TEE High-Level Interaction